Technical Field
Embodiments of the present disclosure are directed to massively parallel supercomputers made from multi-core processor chips.
Discussion of the Related Art
Contemporary supercomputers typically use thousands of processors that are either distributed across a network or are placed in close proximity to each other as in a centralized computer cluster. More recently, supercomputers have started using multi-core processors, with the idea of developing a supercomputer on a chip. The bisectional bandwidth between separate processor chips in a supercomputer is typically limited by the speed and number of electrical links which can be provided between the processors. The available bandwidth between processors on the same chip is significantly higher than what can typically be provided between processors on different chips. The size of individual chips is limited by lithographic field size, yield, and chip packaging technology, and the number of electrical connections between chips is also limited by chip packaging technology. Electrical interconnects within a chip are cheaper and use less power than electrical interconnects between chips on the same substrate, which are cheaper and use less power than electrical interconnects between substrates, etc. A number of useful computational tasks can be limited by the available bisectional bandwidth, such as sparse matrix multiplication used in natural language processing, or large fast Fourier transforms (FFTs).